Design Infrastructure Alley 2018 Speaking Schedule
Three Days of Insightful, Thought-Provoking Content on Engineering IT Infrastructure Topics
This year’s DAC will have the Design Infrastructure Alley, a section of DAC devoted to the infrastructure required to design chips and systems. The premise for the DIA is pretty simple:
Every year we get together at DAC to talk about new tools and new methods to create more complex chips and systems. But we never talk about the infrastructure needed to use these new methods and tools. The Design Infrastructure Alley bridges the gap between potential and execution and allows IT Professionals, Engineers and EDA Suppliers to have a conversation about how best to enable Design.
Below is the speaking schedule for this year’s Inaugural Design Infrastructure Alley. We’re still working through some details regarding topic titles, and we do have one “surprise” guest which will be revealed soon. All of these speakers will be at the Design on Cloud Pavilion on the main Exhibit Floor. You can see the floorpan here to know where you’re going in advance.
|10:30-11:15||Association of HPC Pros: Intro to DIA||Metrics.ca: Verification 3.0 -- Enabling Innovation via the Cloud||Dell EMC: Peeling the onion: how enterprise storage limits tool performance and what you need to do to fix it|
|11:30-12:15||Si2: Si2 OpenAccess—Design Infrastructure for the Future||Altair: Cloud for Cloud Skeptics||Pure Storage: Faster Time to Market: Eliminate Data Bottlenecks for EDA and AI Workloads|
|12:30-1:30||Microsoft / Azure: Why Cloud, Why Now?||Cadence: EDA on the Cloud: Are We Ready?||FootPrintKu PalPilot: Influencing Design Libraries with Cloud Automation|
|1:30-2:15||IC Manage: 10 minutes to Hybrid Cloud Bursting – Run Existing Workflows in the Cloud without Retooling||Google: Moving EDA to the Cloud - a Google-on-Google story||TI: CPU Oversubscription in Compute Clouds|
|2:30-3:15||IBM: EDA on IBM Cloud||Univa: Towards a Strategic Deployment Pattern for the EDA Hybrid Cloud||Ellexus: Fast, Agile and Cloud Ready: How to make workflows faster and easier to move|
|3:30-4:15||ACM: Design for Security: A High-Level Synthesis Approach||AWS: Innovation at Cloud Speed for IoT, AI, and Semiconductor Design||Alibaba: Alibaba Eco-System Enable Your Business|
|4:30-5:30||Panel - Cloud: Cloud Computing for EDA: Pie in the Sky or Pie in the Face||Six Nines: Revolutionizing semiconductor design workflows with HPC in the cloud||SuSE|
There will also be a CELUG Meeting, focusing specifically on license topics which will occur on Tuesday, June 26 in a separate room. You must register for this conference separately, and the cost is only $100. The agenda for the CELUG conference is still under construction, so there may be some minor changes to it. Double-check this page to see the latest.
Special thanks to our friends at OpenIT for sponsoring lunch at the CELUG Conference! Your generous donation is much appreciated!
|9:00 - 9:30||Ansys|
|9:30 - 10:00||Mathworks|
|10:00 - 10:30||Mentor Graphics, a Seimens Business|
|10:30 - 11:00||Cadence|
|11:00 - 11:30||Synopsys|
|11:30 - 1:00||Lunch Break|
|1:00 - 1:30||Flexera, Flexnet Publisher|
|1:30 - 2:00||Flexnet Manager for Engineering Applications|
|2:00 - 3:00||Machine Certification Discussion|
|3:00 - 4:00||CELUG Only Session|